A phase shift keying device is a device generally integrated in a receiver. It notably allows the phase modulation information to be extracted from the carrier wave of a received signal. The phase modulation information is typically delivered by such a device in the form of an electrical signal with a voltage proportional to the phase shift introduced by the transmitter device that has generated and transmitted the received signal.
In the prior art various embodiments of a demodulator device for the phase of a carrier wave exist. These embodiments may notably be divided into three main categories depending on the ratio of the data rate of the information conveyed by the signal received on the one hand and the frequency of the carrier wave of the signal received on the other.
When this ratio is appreciably less than 1%, the device for demodulating the phase of a carrier wave is produced according to an architecture comprising one or more phase locked loops or one or more sensors in quadrature. Such devices comprise filters and mixers.
When this ratio is approximately between 1% and 10%, the device for demodulating the phase of a carrier wave is produced according to an architecture comprising one or more phase locked loops or a ramp-based architecture, qualified as “direct”. The direct ramp-based architecture is detailed notably in the communication by D. Caucheteux, E. Beigné, M. Renaudin and E. Crochon entitled “A New Class of Asynchronous Inductive Contactless Devices Using Event Based Communications and Self-Timed Logic”, IFIP International Conference on Very Large Scale Integration, VLSI-SoC'05, Perth Australia, 17-19 Oct. 2005.
When this ratio is appreciably more than 10%, the device for demodulating the phase of a carrier wave is produced according to a direct ramp-based architecture. The field of application is then restricted to HF and VHF frequencies.
Numerous technological constraints constrain the design of devices for demodulating the phase of a carrier wave, notably when this ratio is high, for example equal to 37.5% in the RFID application described below. Thus silicon integration technologies require operating at low power-supply voltages, typically 1.2V for a technology with an etching resolution that allows an MOS transistor gate width of 130 nm to be attained. The dynamic voltage of such a device may be defined as the difference between the voltage generated by the device when the phase of the received signal reaches its maximum on the one hand and the voltage generated by said device when the phase of the received signal reaches its minimum on the other hand. The dynamic voltage is notably linked with the voltage resolution and with the number of phase-coding bits. The minimum acceptable resolution is fixed by the minimum noise margin necessary to the application and to a lesser extent by the constraints of the design of the analogue-to-digital converter. In order to increase the data rate when the duration of the symbol time depends on the application and when the minimum resolution is fixed by the constraints of design, the number of phase-coding bits must be increased: the dynamic voltage then increases by a ratio that is a power of 2. For a high data rate, i.e. of around 5 Mbits/s, the ratio of the power-supply voltage of said device to the dynamic voltage of said device (before the analogue-to-digital conversion) must therefore be close to 1.
The document U.S. Pat. No. 5,990,733A discloses a PSK demodulator comprising a ramp-based system. The PSK demodulator delivers an output signal with a voltage that remains constant or varies depending on whether the periods of two consecutive cycles of the signal are identical or vary. The amplitude of these variations depends, among other things, on the phase jump programmed in the transmitter and on the bandwidth of the radiofrequency or inductive connection (transmitter and receiver antennas, channel). However, as described in more detail below, this PSK demodulator only exploits a fraction of the modulation amplitude and proves poor in performance, unusable even when a high data rate is desired. This is all the more critical when the power-supply voltages of the demodulator are low.